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Genesys Logic, Inc.
GL813 USB 2.0 CompactFlash Card Reader Controller
Specification 1.2
April 12, 2002
Genesys Logic, Inc. 10F., No.11, Ln.155, Sec.3, Peishen Rd., Shenkeng, Taipei, Taiwan Tel: 886-2-2664-6655 Fax: 886-2-2664-5757 http://www.genesyslogic.com
GL813 - USB2.0 CompactFlash Card Reader Controller
Contents
1. General Description ......................................................................................... 3 2. Features ............................................................................................................ 4 3. Function Block ................................................................................................. 5 3.1 Block Diagram .............................................................................................. 5 3.2 Functional Overview ..................................................................................... 6 4. Pinning Information ......................................................................................... 7 4.1 48-pin LQFP Package .................................................................................. 7 4.2 100-pin LQFP package................................................................................. 9 5. Functional Description .................................................................................. 15 5.1 Transmit Operation ..................................................................................... 15 5.2 Receive Operation...................................................................................... 17 6. Electrical Characteristics .............................................................................. 19 6.1 Absolute Maximum Ratings ........................................................................ 19 6.2 Recommended Operating Conditions......................................................... 19 6.3 DC Characteristics (Digital Pins) ................................................................ 19 6.4 DC Characteristics (D+/D-)......................................................................... 20 6.5 Switching Characteristics ........................................................................... 20 7. Package Dimension ....................................................................................... 22 7.1 48-pin LQFP Package ................................................................................ 22 7.2 100-pin LQFP Package .............................................................................. 23 8. Revision History............................................................................................. 24
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 2 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
1. General Description
The GL813 is a high performance, low cost USB2.0 CompactFlash-single card reader controller. With the integration of GenesysLogic own design USB 2.0 high speed UTMI transceiver, the GL813 has made a conspicuous improvement with full speed USB 1.1 card readers on data transfer rate between PC host and flash memory card. There are totally 4 endpoints in GL813 controller, Control, Bulk In, Bulk Out, and Interrupt. Complies with USB 480Mbps specification ver. 2.0 and USB Storage Class specification ver. 1.0. (Bulk only protocol), the GL813 can support not only plug and play but also Windows ME/ 2000/ XP default driver. For the EMI consideration, the GL813 uses 12MHZ crystal and slew-rate controlled pads to reduce the EMI issue. The GL813 is 48-pin LQFP package (9mmX9mm) to make the best cost competitive for the high speed single flash card reader design and applications. Also we provide 100-pin LQFP package (14mmX14mm) with external ROM/ Flash for design flexibility.
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
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GL813 - USB2.0 CompactFlash Card Reader Controller
2. Features
Complies with Universal Serial Bus specification rev. 2.0. Complies with Compact Flash specification rev. 1.4. Complies with USB Storage Class specification ver.1.0. (Bulk only protocol) Operating system supported: Win XP/ 2000/ ME/ 98/ 98SE; Mac OS 9.X/ X. Supports 4 endpoints: Control/ Bulk Read/ Bulk Write/ Interrupt. 64/ 512 bytes Data Payload for full / high speed Bulk Endpoint. Supports 8-bit / 16-bit Standard PIO mode interface. Embedded USB 2.0 UTMI transceiver. Embedded 7.5 MIPS RISC CPU. Supports external ROM/ Flash modes for design flexibility. (100-pin LQFP) Supports Power Down mode and USB suspend indicator. Supports USB 2.0 TEST mode features. 12MHz external clock to provide better EMI3.3V power input. 5V tolerance pad for Compact Flash Card interface. Supports EEPROM to customize USB VID / PID and String Descriptors. Available in 48-pin (9mmX9mm) / 100-pin (14mmX14mm) LQFP package.
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 4 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
3. Function Block
3.1 Block Diagram
CPU
Control Register
CONTROL FIFO
Compact Flash Controller Engine
TXFIFO0
TXFIFO1
SIE
UTMI LOGIC
USB2.0 TXCVR
RXFIFO0
RXFIFO1
12MHz
X40 Clkgen
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
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GL813 - USB2.0 CompactFlash Card Reader Controller
3.2 Functional Overview
3.2.1 USB 2.0 TXCVR The USB 2.0 Transceiver is the analog circuitry to handle the USB HS/FS signaling. 3.2.2 UTMI Logic The UTMI Logic is compliant to Intel's UTMI specification 1.01. This block handles the low level USB protocol and signaling. The major jobs of UTMI Logic is data and clock recovery, NRZI encoding/decoding, Bit Stuffing/De-stuffing, USB2.0 test modes supporting and serial / parallel conversion. 3.2.3 PLL 40XPLL block will provide 480MHz for USB HS data transmission. 3.2.4 CLKGEN CLKGEN is the clock generator block for the logic blocks. It generates 15MHz clock for micro controller, 12MHz for PIO mode, and 30MHz clock for UTMI, SIE, and FIFO. 3.2.5 CPU The CPU is the control center of GL813. It's an 8-bit micro controller operating in 15MHz, 7.5 MIPS. After receiving a USB command, it decodes the host command, then it re-assigns tasks to the CompactFlash controller engine, GPIO, FIFO, and response proper data/ status to USB host. 3.2.6 CompactFlash Controller Engine The CompactFlash controller engine is extended from standard ATA/ ATAPI protocol. It supports PIO mode data transfers. 3.2.7 FIFOs Control FIFO is used as Control Read / Write FIFO. TXFIFO0 / TXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Read endpoint. It buffers data from CompactFlash controller engine, and re-direct to USB SIE logic. RXFIFO0 / RXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Write endpoint. It buffers data from USB SIE logic, and re-direct to CompactFlash controller engine. 3.2.8 Control Registers Control Register configures GL813 to proper operation. For example, CPU can set register to generate wakeup event, enter suspend, transmits proper USB packet to host.
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
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GL813 - USB2.0 CompactFlash Card Reader Controller
4. Pinning Information
4.1 48-pin LQFP
IODD[7]
IODD[6]
IODD[5]
IODD[4]
IODD[3]
IODD[2]
IODD[1] 38
48
47
46
45
44
43
42
41
40
39
37 AVCC1 24
IODD[0]
DGND2
DVCC2
CFRST
CS
CFPWR IODD[8] IODD[9] IODD[10] IODD[11] DVCC1 DGND1 IODD[12] IODD[13] IODD[14] !ODD[15] DO
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33
DIOW_ DIOR_ IORDY INTRQ DA1/ Dl DA0 CS0_ TEST CFDET AGND1 X1 X2
GL813 48 LQFP
32 31 30 29 28 27 26 25
13
14
15
16
17
18
19
20
21
22 AGND0
DMF
DPF
RESET#
Pin # 1 2~5 6 7 8~11 12 13
Name CFPWR IODD [8:11] DVCC1 DGND1 IODD [12:15] DO CS1_
DA2/ SK
I/O B I P P B I O
AVCC0
Pad Type Tri-state Tri-state Power Power Tri-state Tri-state Tri-state
RREF
RPU
DPH
CS1_
DMH
23
Description Compact flash card power control IDE data bus 8~11 Digital VCC Digital ground IDE data bus 12~15 DO from EEPROM IDE chip select 1
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
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GL813 - USB2.0 CompactFlash Card Reader Controller
Pin # 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37~40 41 42 43~46 47 48 DA2 / SK RESET# RPU AVCC0 DPF DPH DMF DMH AGND0 RREF AVCC1 X2 X1 AGND1 CFDET TEST CS0_ DA0 DA1 / DI INTRQ IORDY DIOR_ DIOW_
Name
I/O O I A P B B B B P P B I P I I O O O I I O O B P P B O B
Pad Type Tri-state Pull-high U20mia Power U20mia U20mia U20mia U20mia Power U20mia Power Clock Clock Power Tri-state Pull-low Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Power Power Tri-state Tri-state Tri-state
Description IDE address 2 / SK to EEPROM HW reset 3.3v output Analog VCC Full speed DP High speed DP Full speed DM High speed DM Analog ground Reference resister connect (*) Analog VCC Crystal output Crystal input, 12Mhz Analog ground Compact flash card detect TEST mode input IDE Chip select 0 IDE address 0 IDE address 1 / DI to EEPROM IDE Interrupt request IDE IO ready IDE read signal IDE write signal IDE data bus 0~3 Digital ground Digital VCC IDE data bus 4~7 CS to EEPROM Compact Flash Card HW reset
IODD [0:3] DGND2 DVCC2 IODD [4:7] CS CFRST
(*) RREF must be connected with a 510 ohm resister to ground.
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 8 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
4.2 100-pin LQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GPIO7 GPIO4 GPIO3 GPIO2 GPIO1 IODD7 IODD6 IODD5 IODD4 DVCC2 DGND2 IODD3 IODD2 IODD1 IODD0 DMARQ GPIO9 GPIO10 GPIO11 GPIO12 NC NC NC NC DIOW_
NC NC NC NC GPIO8 GPIO5 GPIO6 IODD8 IODD9 IODD10 IODD11 DVCC1 NC NC DGND1 IODD12 IODD13 IODD14 IODD15 CBLID_ EXT0 EXT1 EXT2 EXT3 EXT4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
GL813 100 LQFP
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
EXT5 NC NC NC NC EXT6 EXT7 EXT8 EXT9 EXT10 EXT11 EXT12 EXT13 CS1_ DA2 RESET# RPU AVCC0 DPF DPH DMF DMH AGND0 RREF AVCC1
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC DIOR_ IORDY DMACK_ INTRQ GPIO13 GPIO14 GPIO15 GPIO16 DA1 DA0 CS0_ GPIO17 GPIO18 GPIO19 EXT15 EXT14 NC AGND1 X1 X2 NC NC NC NC
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GL813 - USB2.0 CompactFlash Card Reader Controller
Pin # 1 2 3 4 5 6 7 8~11 12 13 14 15 16~19 20 NC NC NC NC GPIO8 GPIO5 GPIO6
Name
I/O B B B B P P B I
Pad Type Tri-state Tri-state Tri-state Tri-state Power Power Tri-state Tri-state GPIO8 (*) GPIO5 GPIO6
Description
IODD [8:11] DVCC1 NC NC DGND1 IODD [12:15] CBLID_
IDE data bus 8 ~ 11 Digital VCC Digital ground IDE data bus 12 ~ 15 Cable select input NC: Embedded CPU mode ECPURD: Read signal when external CPU mode EROMD0: Data0 when external ROM mode NC: Embedded CPU mode ECPUWR: Write signal when external CPU mode EROMD1: Data1 when external ROM mode NC: Embedded CPU mode ECPUA5: Address5 when external CPU mode EROMD2: Data2 when external ROM mode NC: when embedded CPU mode ECPUA4: Address4 when external CPU mode EROMD3: Data3 when external ROM mode NC: Embedded CPU mode ECPUA3: Address3 when external CPU mode EROMD4: Data4 when external ROM mode
21
NC/ECPURD/EROMD0
I
Pull-low
22
NC/ECPUWR/EROMD1
I
Pull-low
23
NC/ECPUA5/EROMD2
I
Pull-low
24
NC/ECPUA4/EROMD3
I
Pull-low
25
NC/ECPUA3/EROMD4
I
Pull-low
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 10 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
Pin #
Name
I/O
Pad Type
Description NC: Embedded CPU mode ECPUA2: Address2 when external CPU mode EROMD5: Data5 when external ROM mode NC: Embedded CPU mode ECPUA1: Address1 when external CPU mode EROMD6: Data6 when external ROM mode NC: Embedded CPU mode ECPUA0: Address0 when external CPU mode EROMD7: Data7 when external ROM mode NC: Embedded CPU mode ECPUD7: Data7 when external CPU mode EROMD8: Data8 when external ROM mode NC: Embedded CPU mode ECPUD6: Data6 when external CPU mode EROMD9: Data9 when external ROM mode NC: Embedded CPU mode ECPUD5: Data5 when external CPU mode EROMD10: Data10 when external ROM mode NC: Embedded CPU mode ECPUD4: Data4 when external CPU mode EROMD11: Data11 when external ROM mode NC: Embedded CPU mode ECPUD3: Data3 when external CPU mode EROMD12: Data12 when external ROM mode
26
NC/ECPUA2/EROMD5
I
Pull-low
27 28 29 30
NC NC NC NC
-
-
31
NC/ECPUA1/EROMD6
I
Pull-low
32
NC/ECPUA0/EROMD7
I
Pull-low
33
NC/ECPUD7/EROMD8
B
Pull-low
34
NC/ECPUD6/EROMD9
B
Pull-low
35
NC/ECPUD5/EROMD10
B
Pull-low
36
NC/ECPUD4/EROMD11
B
Pull-low
37
NC/ECPUD3/EROMD12
B
Pull-low
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 11 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
Pin #
Name
I/O
Pad Type
Description NC: Embedded CPU mode ECPUD2: Data2 when external CPU mode EROMD13: Data13 when external ROM mode Chip select 1 IDE address 2 Reset pin 3.3v output Analog VCC Full speed DP High speed DP Full speed DM High speed DM Analog ground Reference resister connect (*) Analog VCC Crystal output Crystal input, 12Mhz Analog ground NC: Embedded CPU mode ECPUD1: Data1 when CPU mode EROMA0: Address0 when ROM mode NC: Embedded CPU mode ECPUD0: Data0 when CPU mode EROMA1: Address1 when ROM mode GPIO19 GPIO18: for embedded or CPU mode EROMA11: Address11 external ROM mode external external
38
NC/ECPUD2/EROMD13
B
Pull-low
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
CS1_ DA2 RESET# RPU AVCC0 DPF DPH DMF DMH AGND0 RREF AVCC1 NC NC NC NC X2 X1 AGND1 NC
O O I A P B B B B P P B I P -
Tri-state Tri-state Pull-high U20mia Power U20mia U20mia U20mia U20mia Power U20mia Power Clock Clock Power -
59
NC/ECPUD1/EROMA0
B
Pull-low
external external
60
NC/ECPUD0/EROMA1
B
Pull-low
61 62
GPIO19 GPIO18/GPIO18/EROM A11
B B
Pull-low Pull-low
external when
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 12 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
Pin #
Name
I/O
Pad Type
Description GPIO17: For embedded or external CPU mode EROMA10: Address10 when external ROM mode Chip select 0 IDE address 0 IDE address 1 GPIO16: For embedded or external CPU mode EROMA9: Address9 when external ROM mode GPIO15: For embedded or external CPU mode EROMA8: Address8 when external ROM mode GPIO14: For embedded or external CPU mode EROMA7: Address7 when external ROM mode GPIO13: For embedded or external CPU mode EROMA6: Address6 when external ROM mode IDE interrupt input IDE acknowledge IDE ready IDE read signal IDE write signal GPIO12: For embedded or external CPU mode EROMA5: Address5 when external ROM mode GPIO11: For embedded or external CPU mode EROMA4: Address4 when external ROM mode
63
GPIO17/GPIO17/EROM A10 CS0_ DA0 DA1 GPIO16/GPIO16/EROM A9
B
Pull-low
64 65 66 67
O O O B
Tri-state Tri-state Tri-state Pull-low
68
GPIO15/GPIO15/EROM A8
B
Pull-low
69
GPIO14/GPIO15/EROM A7
B
Pull-low
70 71 72 73 74 75 76 77 78 79 80 81
GPIO13/GPIO14/EROM A6 INTRQ DMACK_ IORDY DIOR_ NC DIOW_ NC NC NC NC GPIO12/GPIO13/EROM A5
B I O I O O B
Pull-low Tri-state Tri-state Pull-high Tri-state Tri-state Pull-low
82
GPIO11/GPIO12/EROM A4
B
Pull-low
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 13 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
Pin #
Name GPIO10/GPIO10/EROM A3
I/O
Pad Type
Description GPIO10: For embedded or CPU mode EROMA3: Address3 when ROM mode GPIO9: For embedded or CPU mode EROMA2: Address2 when ROM mode IDE request IDE data bus 0~3 Digital ground Digital VCC IDE data bus 4~7 GPIO1 GPIO2 GPIO3 GPIO4 GPIO 7 (*) external external external external
83
B
Pull-low
84 85 86~89 90 91 92~95 96 97 98 99 100
GPIO9/GPIO9/EROMA2 DMARQ IDEDD [0:3] DGND2 DVCC2 IDEDD [4:7] GPIO1 GPIO2 GPIO3 GPIO4 GPIO7
B I B P P B B B B B B
Pull-low Pull-low Tri-state Power Power Tri-state Pull-high Pull-high Pull-high Pull-low Pull-low
(*) When operating in default mode: GPIO7 is the IDE reset input, GPIO8 is used to control the power input of IDE device.
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 14 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
5. Functional Description
5.1 Transmit Operation
5.1.1 Transmit State Diagram
!TXVLD HRST# Reset !TXRDY !HRST#
TX Wait
TXVLD
TX Hold Reg Empty TX Data Load !TXVLD TXRDY TX Hold Reg Full TX Data Wait !TXRDY TX Hold Reg Empty TX Hold Reg Full
EOP not done Send EOP !TXRDY
Send SYNC
Transmit must be asserted to enable any transmissions. The SIE asserts TXVLD to begin a transmission. The SIE negates TXVLD to end a transmission. After the SIE asserts TXVLD it can assume that the transmission has started when it detects TXRDY asserted. The SIE assumes that the UTM has consumed a data byte if TXRDY and TXVLD are asserted. The SIE must have valid packet information (PID) asserted on the Data bus coincident with the assertion of TXVLD. Depending on the UTM implementation, TXRDY may be asserted by the Transmit State Machine as soon as one CLK after the assertion of TXVLD. TXVLD and TXRDY are sampled on the rising edge of CLKOUT. The Transmit State Machine does not automatically generate Packet ID's (PIDs) or
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 15 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
CRC. When transmitting, the SIE is always expected to present a PID as the first byte of the data stream and if appropriate, CRC as the last bytes of the data stream. The SIE must use LINEST0/1 to verify a Bus Idle condition before asserting TXVLD in the TX Wait state. 5.1.2 Transmit Timing for Data Packet
CLKOUT TXVLD Data TXRDY DP/DM
SYNC PID Data Data Data Data CRC CRC EOP PID Data Data Data Data CRC CRC
C
C
P
The SIE negates TXVLD to complete a packet. Once negated, the Transmit State Machine will never reassert TXRDY until after the EOP has been loaded into the Transmit Shift Register. Note that the UTM Transmit State Machine can be ready to start another package immediately, however the SIE must confirm to the minimum inter-packet delays identified in the USB 2.0 Specification.
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 16 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
5.2 Receive Operation
5.2.1 Receive State Diagram
!SYNC Reset !RXACTV !RXVLD SYNC Detected Data Trip SYNC RXACTV Rx Data RXVLD Receive Error Error RXERR !Data !Idle state !HRST# RX Wait Strip EOP !RXACTV !RXVLD Idle state Terminate !RXACTV
HRST#
EOP Detected
Data
Abort 1 !RXACTV !RXVLD !RXERR
!Data SYNC
Data
RX Data Wait !RXVLD
Abort 2 !RXVLD !RXERR
RXACTV and RXVLD are sampled on the rising edge of CLKOUT. In the RX Wait state the receiver is always looking for SYNC. The Macrocell asserts RXACTV when SYNC is detected (Strip SYNC state). The Macrocell negates RXACTV when an EOP is detected (Strip EOP state). When RXACTV is asserted, RXVLD will be asserted if the RX Holding Register is full. RXVLD will be negated if the RX Holding Register was not loaded during the previous byte time. This will occur if 8 stuffed bits have been accumulated. The SIE must be ready to consume a data byte if RXACTV and RXVLD are asserted (RX Data state). In FS mode, if a bit stuff error is detected then the Receive State Machine will negate RXACTV and RXVLD, and return to the RXWait state.
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 17 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
5.2.2 Receive Timing for Data Packet (with CRC-16)
CLKOUT RXACTV Data RXVLD RXERR DP/DM
SYNC PID Data Data Data Data CRC CRC EOP PID Data Data Data Data CRC CRC
Note that the USB 2.0 transceiver does not decode Packet ID's (PIDs). They are passed to the SIE for decoding. This timing example is in HS mode. When a HS/FS UTM is in FS mode there are approximately 40 clock cycles every byte time. The Receive State Machine assumes that the SIE captures the data on the data bus if RXACTV and RXVLD are asserted. In FS mode, RXVLD will only be asserted for one clock per byte time. Note that the receive and transmit sections of the transceiver operate independently. The receiver will receive any packets on the USB. The transceiver does not identify whether the packet that it is receiving from the upstream or the downstream port. The SIE must ignore receive data while it is transmitting.
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 18 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
6. Electrical Characteristics
6.1 Absolute Maximum Ratings
Symbol VCC VI VI/O VAI/O VI/OZ VESD TA Description DC supply voltage DC input voltage DC input voltage range for I/O DC input voltage for USB D+/D- pins DC voltage applied to outputs in High Z state Static discharge voltage Ambient Temperature Min -0.3 -0.3 -0.3 -0.3 -0.3 4000 0 100 Max +3.6 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 Unit V V V V V V
o
C
6.2 Recommended Operating Conditions
Item Supply Voltage Ground Voltage Fosc Operating Temperature Value +3.3V to + 3.6V 0V 12 MHz 100 ppm 0 oC ~ 70 oC
6.3 DC Characteristics (Digital Pins)
Symbol PD VDD IO VIL VIH VTLH VTHL Description Power Dissipation Power Supply Voltage DC output sink current excluding D+/ D-/ VCC/ GND LOW level input voltage HIGH level input voltage LOW to HIGH threshold voltage HIGH to LOW threshold voltage 2.0 1.3 1.3 1.43 1.43 1.56 1.56 3 8 0.9 3.3 3.6 Min Typ Max Unit mA V mA V V V V
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 19 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
Symbol VHYS VOL VOH IOLK RDN RUP
Description Hysteresis voltage LOW level output voltage when IOL=8mA HIGH level output voltage when IOH=8mA Leakage current for pads with internal pull up or pull down resistor Pad internal pull down resister Pad internal pull up resister
Min -
Typ 0
Max 0.4
Unit V V V
2.4 46 79K 78K 105K 104K 152K 146K
A Ohms Ohms
6.4 DC Characteristics (D+/D-)
Symbol VOL VOH VDI VCM VSE CIN ILO ZDRV Description D+/D- static output LOW (RL of 1.5K to 3.6V ) D+/D- static output HIGH (RL of 15K to GND ) Differential input sensitivity Differential common mode range Single-ended receiver threshold Transceiver capacitance Hi-Z state data line leakage Driver output resistance -10 28 2.8 0.2 0.8 0.2 20 +10 43 2.5 Min Typ Max 0.3 3.6 Unit V V V V V pF A Ohms
6.5 Switching Characteristics
Symbol FX1 TCYC TX1L TX1H Tr30pf Tf30pf Description X1 crystal frequency X1 cycle time X1 clock LOW time X1 clock HIGH time Output pad rise time from 10% to 90% swing with 30pF loading Output pad fall time from 10% to 90% swing with 30pF loading 0.45Tcyc 0.45Tcyc Min 11.97 Typ 12 83.3 Max 12.03 Unit MHz ns ns ns ns ns
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 20 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
Symbol Tr50pf Tf50pf TrUSB TfUSB
Description Output pad rise time from 10% to 90% swing with 50pF loading Output pad fall time from 10% to 90% swing with 50pF loading D+/D- rise time with 50pF loading D+/D- fall time with 50pF loading
Min
Typ
Max
Unit ns ns
4 4
20 20
ns ns
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 21 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
7. Package Dimension
7.1 48-pin LQFP
SYMBOL
A A1 A2 C1 D D1 E E1 e b L L1
MIN
MAX
1.6
0.05 1.35 0.09 9.00BSC 7.00BSC 9.00BSC 7.00BSC 0.5BSC 0.17 0.45 1 REF
0.15 1.45 0.16
0.27 0.75
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
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GL813 - USB2.0 CompactFlash Card Reader Controller
7.2 100-pin LQFP
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
Page 23 of 24
GL813 - USB2.0 CompactFlash Card Reader Controller
8. Revision History
Version 1.0 1.1 1.2 First draft Correction and supplement of Electrical Characteristics data Add 100-pin LQFP package related data Description Date 2002/03/20 2002/04/03 2002/04/12
(c)2001-2002 Genesys Logic Inc.--All rights reserved.
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